Semiconductor integrated circuit device and method for manufacturing the same

ABSTRACT

The sheet resistance of a gate electrode  8 A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL 1 , BL 2  are, respectively, 2 Ω/□ or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode  8 A (the word line WL) or the bit lines BL 1 , BL 2  by which the number of the steps of manufacturing the DRAM can be reduced.

[0001] This application is a continuation of U.S. application Ser. No.09/714,127, filed Nov. 17, 2000, which, in turn, is a continuation ofU.S. application Ser. No. 08/782,351, filed Jan. 13, 1997, and now U.S.Pat. No. 6,150,689, and the entire disclosures of which are herebyincorporated by reference.

BACKGROUND OF THE INVENTION

[0002] This invention relates to a semiconductor integrated circuitdevice and also to a method for manufacturing the same. Moreparticularly, the invention relates to a technique which is suitablyapplicable to semiconductor integrated circuit devices which include aDRAM (dynamic random access memory) provided with a memory cell having astacked capacitor structure wherein an information storage capacitor isarranged above a MISFET for memory cell selection.

[0003] The recent DRAM with a great capacity usually has a stackedcapacitor structure, wherein an information storage capacitor isarranged above a memory cell selection MISFET, in order to compensatefor a storage charge reduction of an information storage capacitor aswill be caused by the miniaturization of the memory cells.

[0004] The information storage capacitor having the stacked capacitorstructure is formed by successively superposing a storage electrode(lower electrode), a capacity insulating film (dielectric film), and aplate electrode (upper electrode). The storage electrode of theinformation storage capacitor is connected with one of the semiconductorregions (source region, drain region) of a memory selection MISFET ofthe n channel type. The plate electrode is constituted as a commonelectrode for a plurality of memory cells and is supplied with a givenfixed potential (plate potential).

[0005] The other semiconductor region (source region, drain region) ofthe memory cell selection MISFET is, in turn, connected to a bit line inorder to permit data to be written in and read out. The bit line isprovided between the MISFET for memory cell selection and theinformation storage capacitor or above the information storagecapacitor. The structure wherein the information storage capacitor isprovided above the bit lines is called a “capacitor over bitline” (COB)structure.

[0006] A DRAM having such a COB structure is described, for example, inJapanese Laid-open Patent Application No. 7-122654 (corresponding to aU.S. patent application Ser. No. 08/297,039, assigned to Hitachi Ltd.),and Japanese Laid-open Patent Application No. 7-106437.

[0007] The DRAM disclosed in the Japanese Laid-open Patent ApplicationNo. 7-122654 includes bit lines which are formed of a polysilicon film(or polycide film) formed above the MISFET for memory cell selectionwherein a gate electrode (word line) is formed of a built-up film(polycide film) of a polysilicon film and a tungsten silicide (WSi_(x))film. An information storage capacitor which includes a storageelectrode formed of a polysilicon, a capacitance insulating filmconstituted of a built-up film of a silicon oxide film and a siliconnitride film, and a plate electrode formed of a polysilicon film areprovided above the bit lines. In addition, a common source line made ofa first layer made of an Al (aluminum) film and a word line for a shuntare formed over the information storage capacitor.

[0008] The DRAM set out in the Japanese Laid-open Patent Application No.7-106437 includes bit lines made of a polysilicide film and formed onthe MISFET for memory cell selection whose gate electrode (word line) ismade of a polysilicon film. The storage electrode or plate electrode ofthe information storage capacitor disposed above the bit lines and thefirst interconnection layer of a peripheral circuit are both formed of ametal material (e.g. Pt). Thus, the step of forming the electrode of theinformation storage capacitor and the step of forming the metallicinterconnection of the peripheral circuit are performed commonly tosimplify the manufacturing process.

SUMMARY OF THE INVENTION

[0009] The DRAM having the COB structure includes a gate electrode (wordline) formed of polysilicon or polycide which has a resistance greaterthan metallic materials such as Al or W, so that a metallicinterconnection (a word line for shunt) for backing the gate electrodeis formed above the information storage capacitor, thereby reducing thedelay of the gate. Since the bit line is constituted of polycide whichis unable to simultaneously connect n-type and p-type semiconductorregions therewith, it is not possible to use a common interconnectionfor the bit lines and the peripheral circuit. To avoid this, the numberof interconnection layers for both the memory arrays and the peripheralcircuit increases, thus presenting a problem of increasing the number ofmanufacturing steps.

[0010] The common use of the interconnections for the bit lines and theperipheral circuit is not possible, so that the first interconnectionlayer of the peripheral circuit has to be formed as an upper layerrelative to the bit lines. This causes a great aspect ratio(diameter/depth) of a connection hole for connecting the firstinterconnection layer and the MISFETs of the peripheral circuit, withthe attendant problem that the formation of the connection hole becomesdifficult and it also becomes difficult to embed or fill aninterconnection material in the connection hole.

[0011] Where the gate electrode (word line) is formed of polysilicon orpolycide with a high resistance, it is not possible to increase thenumber of memory cells capable of connection with one word driver orsense amplifier. More particularly, in order to reduce the delay of thegate, an increasing number of word drivers or sense amplifiers arenecessary for connection to a given number of memory cells, so thatthere arises the problem that the chip size has to be increased,resulting in the lowering in degree of integration.

[0012] An object of the invention is to provide a technology capable ofsimplifying a process of manufacturing a DRAM having the COB structure.

[0013] Another object of the invention is to provide a technology forachieving a high-speed DRAM having the COB structure.

[0014] A further object of the invention is to provide a technology forachieving a high performance DRAM having the COB structure.

[0015] A still further object of the invention is to provide atechnology for achieving a highly integrated DRAM having the COBstructure.

[0016] The above and other objects, and features of the invention willbecome apparent from the description with reference to the accompanyingdrawings.

[0017] Typical inventions in this application are summarized below.

[0018] The semiconductor integrated circuit device according to oneaspect of the inventions comprises a DRAM which includes a memory cellconstituted of a MISFET for memory cell selection and an informationstorage capacitor formed on the MISFET, wherein a sheet resistance of agate electrode of the MISFET for memory cell selection and a word lineconnected thereto, and a sheet resistance of a bit line connected to oneof a source region and a drain region of the MISFET for memory cellselection, are, respectively, 2 Ω/□ or below.

[0019] In the above one aspect of the invention, it is preferred thatthe sheet resistance of the gate electrode of the MISFET for memory cellselection and the word line connected thereto, and the sheet resistanceof the bit line connected to one of a source region and a drain regionof the MISFET for memory cell selection, are, respectively, 1 Ω/□ orbelow.

[0020] It is also preferred that the gate electrode of the MISFET andthe word line connected thereto are, respectively, made of a built-upfilm comprising, at least, a polysilicon film and a metallic film or ametal silicide film formed on the polysilicon film.

[0021] Preferably, the bit line is arranged above or over the MISFET formemory cell selection, and the information storage capacitor is arrangedabove or over the bit line.

[0022] The bit line should preferably be constituted of a built-up filmwhich comprises, at least, a polysilicon film and a metallic film or ametal silicide film formed on the polysilicon film.

[0023] The sheet resistance of the interconnection formed on theinformation storage capacitor should preferably be equal to or smallerthan that of the bit line.

[0024] A given interconnection layer of a peripheral circuit of the DRAMin the semiconductor integrated circuit device of the invention shouldpreferably include an interconnection formed in the same manufacturingstep as the gate electrode of the memory cell selection MISFET and theword line connected thereto.

[0025] A given interconnection layer of a peripheral circuit of the DRAMin the semiconductor integrated circuit device of the invention shouldpreferably include an interconnection formed in the same manufacturingstep as the bit line.

[0026] Preferably, the peripheral circuit of the DRAM is provided with aresistor which is formed in the same manufacturing step as the bit line.

[0027] According to a further aspect of the invention, there is alsoprovided a semiconductor integrated circuit device which comprises aDRAM having a memory cell which includes a MISFET for memory cellselection and an information storage capacitor formed on the MISFET,wherein the information storage capacitor has a storage electrode whosesheet resistance is 2 Ω/□ or below.

[0028] In this further aspect, it is preferred that an interconnectionformed in the same manufacturing step as the storage electrode of theinformation storage capacitor is formed in a given interconnection layerof a peripheral circuit of the DRAM.

[0029] It is also preferred that the peripheral circuit of the DRAM isprovided with a resistor which is formed in the same manufacturing stepas the storage electrode of the information storage capacitor.

[0030] According to a further aspect of the invention, there is provideda semiconductor integrated circuit device which comprises a DRAM havinga memory cell which includes a MISFET for memory cell selection and aninformation storage capacitor formed on the MISFET, wherein theinformation storage capacitor has a plate electrode whose sheetresistance is 2 Ω/□ or below.

[0031] In the further aspect, it is preferred that an interconnectionformed in the same manufacturing step as the plate electrode of theinformation storage capacitor is formed in a given interconnection layerof a peripheral circuit of the DRAM.

[0032] Preferably, the peripheral circuit of the DRAM is provided with aresistor which is formed in the same manufacturing step as the plateelectrode of the information storage capacitor.

[0033] According to a still further aspect of the invention, there isprovided a method for manufacturing a semiconductor integrated circuitdevice which comprises a DRAM which includes a memory cell constitutedof a MISFET for memory cell selection and an information storagecapacitor formed thereon, the method comprising the steps of:

[0034] (a) forming a word line connected to a gate electrode of theMISFET for memory cell selection on a semiconductor substrate whereinthe word line has a sheet resistance of 2 Ω/□ or below; and

[0035] (b) forming a bit line connected to one of a source region and adrain region of the MISFET for memory cell selection on the gateelectrode of the MISFET for memory cell selection and the word lineconnected thereto and having a sheet resistance of 2 Ω/□ or below.

[0036] Preferably, the method further comprises the step of forming aninformation storage capacitor on the bit line wherein at least one of astorage electrode and a plate electrode of the capacitor has a sheetresistance of 2 Ω/□ or below.

[0037] It is also preferred that the method further comprises the stepof forming an interconnection having a sheet resistance, equal to orsmaller than the sheet resistance of the bit line, on the capacitor.

[0038] In the method according to the above aspect of the invention, afirst interconnection layer of a peripheral circuit is formed in thestep (a) or (b).

[0039] Moreover, in the step of forming the storage electrode or theplate electrode of the information storage capacitor, it is preferred toform a second interconnection layer of the peripheral circuit.

[0040] Preferably, a third interconnection layer of the peripheralcircuit is formed over the capacitor in the step of forming aninterconnection and a Y selection line built up on the plate electrodeof the information storage capacitor.

[0041] Preferably, the method of the invention should further comprisethe step of simultaneously forming at least two connection holes among afirst connection hole connecting the third interconnection layer and thesecond interconnection layer, a second connection hole connecting thethird interconnection layer and the first interconnection layer, a thirdconnection hole connecting the second interconnection layer and thefirst interconnection layer, and a fourth connection hole connecting thethird interconnection layer, the second interconnection layer and thefirst interconnection layer, wherein the at least two connection holesare formed in a layer of insulating film for insulating the thirdinterconnection layer and the second interconnection layer from eachother.

[0042] It is also preferred that a dummy interconnection is formed belowthe first connection hole connecting the third interconnection layer andthe second interconnection layer in the same step as the firstinterconnection layer.

[0043] Moreover, a dummy interconnection is preferably formed on the wayof the second connection hole connecting the third interconnection layerand the first interconnection layer in the same step as the secondinterconnection layer.

[0044] Preferably, a dummy interconnection is preferably formed abovethe third connection hole connecting the second interconnection layerand the first interconnection layer in the same step as the thirdinterconnection layer.

[0045] A method for manufacturing a semiconductor integrated circuitdevice according to a further aspect of the invention is characterizedby forming a DRAM having a memory cell constituted of a MISFET formemory cell selection and an information storage capacitor formed on theMISFET, and a logic LSI on the same plane of a semiconductor substrate,wherein a sheet resistance of a gate electrode of the MISFET and a wordline connected thereto, and a sheet resistance of a bit line are,respectively, 2 Ω/□ or below, and a given interconnection of the logicLSI is formed in the same step as the gate electrode of the MISFET andthe word line connected thereto or the bit line.

[0046] Preferably, the above method further comprises forming, on thebit line, an information storage capacitor having a storage electrodeand a plate electrode at least one of which has a sheet resistance of 2Ω/□ or below, and forming the given interconnection of the logic LSIsimultaneously at the step of forming the storage electrode or the plateelectrode.

[0047] According to a further aspect of the invention, there is provideda method for manufacturing a semiconductor integrated circuit device,the method comprising the steps of:

[0048] providing a semiconductor substrate having first and secondportions on the main surface thereof;

[0049] depositing a first conductor layer on the first and secondportions and subjecting the first conductor layer to patterning to forma first interconnection on the first portion and a secondinterconnection on the second portion;

[0050] forming a first insulating film over the semiconductor substrateto cover the first and second interconnections;

[0051] depositing a second conductor layer over the first and secondportions and patterning the second conductor layer to form a thirdinterconnection as superposed on the first interconnection via the firstinsulating film over the first portion and a fourth interconnection assuperposed on the second interconnection via the first insulating filmover the second portion;

[0052] forming a second insulating film over the semiconductor substrateto cover the third and fourth interconnections therewith;

[0053] forming a first connection hole in a portion of the first portionwhere the first and third interconnections are superposed so that thefirst interconnection is exposed on the surface thereof via the secondinsulating film, the third interconnection and the first insulatingfilm, and also a second connection hole in a portion of the secondportion where the second and fourth interconnections are superposed sothat the second interconnection is exposed on the surface thereof viathe second insulating film, the fourth interconnection and the firstinsulating film;

[0054] filling a third conductor layer in the first and secondconnection holes; and

[0055] depositing a fourth conductor layer over the first and secondportions and patterning the fourth conductor layer to form a fifthinterconnection in the first portion to cover the first connection holeand a sixth interconnection in the second portion to cover the secondconnection hole, wherein the third conductor layer in the firstconnection layer electrically connects the first, third and fifthinterconnections therewith and the third conductor layer in the secondconnection hole electrically connects the second and fourthinterconnections therewith and wherein the sixth interconnectionprotects the third conductor layer in the second connection hole at thetime of the patterning of the fourth conductor layer.

[0056] According to a further aspect of the invention, there is provideda method for manufacturing a semiconductor integrated circuit device,the method comprising the steps of:

[0057] providing a semiconductor substrate having first and secondportions on the main surface thereof;

[0058] depositing a first conductor layer on the first and secondportions and subjecting the first conductor layer to patterning to forma first interconnection on the first portion and a secondinterconnection on the second portion;

[0059] forming a first insulating film over the semiconductor substrateto cover the first and second interconnections;

[0060] depositing a second conductor layer on the first and secondportions and patterning the second semiconductor layer to form a thirdinterconnection as superposed on the first interconnection via the firstinsulating film over the first portion and a fourth interconnection assuperposed on the second interconnection via the first insulating filmover the second portion;

[0061] forming a second insulating film over the semiconductor substrateto cover the third and fourth interconnections therewith;

[0062] forming a first connection hole in a portion of the first portionwhere the first and third interconnections are superposed so that thefirst interconnection is exposed on the surface thereof via the secondinsulating film, the third interconnection and the first insulatingfilm, and also a second connection hole in a portion of the secondportion where the second and fourth interconnections are superposed sothat the second interconnection is exposed on the surface thereof viathe second insulating film, the fourth interconnection and the firstinsulating film;

[0063] filling a third conductor layer in the first and secondconnection holes; and

[0064] depositing a fourth conductor layer over the first and secondportions and patterning the fourth conductor layer to form a fifthinterconnection in the first portion to cover the first connection holeand also a sixth interconnection in the second portion to cover thesecond connection hole, wherein the third conductor layer in the firstconnection layer electrically connects the first, third and fifthinterconnections therewith and the third conductor layer in the secondconnection hole electrically connects the second and fourthinterconnections therewith.

[0065] According to a further aspect of the invention, there is provideda method for manufacturing a semiconductor integrated circuit device,the method comprising the steps of:

[0066] providing a semiconductor substrate having first and secondportions on the main surface thereof;

[0067] depositing a first conductor layer on the first and secondportions and subjecting the first conductor layer to patterning to forma first interconnection on the first portion and a secondinterconnection on the second portion;

[0068] forming a first insulating film over the semiconductor substrateto cover the first and second interconnections;

[0069] depositing a second conductor layer on the first and secondportions and patterning the second semiconductor layer to form a thirdinterconnection as superposed on the first interconnection over thefirst portion;

[0070] forming a second insulating film over the semiconductor substrateto cover the third interconnection therewith;

[0071] forming a first connection hole in the first portion so that thesecond interconnection is exposed on the surface thereof and also asecond connection hole in the second portion so that the secondinterconnection is exposed on the surface thereof; and

[0072] depositing a third conductor layer over the first and secondportions and patterning the third conductor layer to form a fourthinterconnection in the first portion to cover the first connection holeand also a fifth interconnection in the second portion to cover thesecond connection hole, wherein the first interconnection is superposedwith the first connection hole on a plane.

[0073] According to a further aspect of the invention, there is provideda method for manufacturing a semiconductor integrated circuit devicewhich comprises a plurality of memory cells including MISFETs for memorycell selection and information storage capacitors connected in series, aplurality of memory cell arrays having a plurality of word lines and aplurality of bit lines mutually extending in parallel to each other, andperipheral circuits located between the plural memory cell arrays, themethod comprising the steps of:

[0074] providing a semiconductor substrate having a first portionwherein memory cell arrays are formed and a second portion whereinperipheral circuits are formed;

[0075] forming a first conductor layer over the semiconductor substrateand patterning the first conductor layer to form a plurality of firstinterconnections to form bit lines in the first portion and second andthird interconnections in the second portion;

[0076] forming a first insulating film on the first, second and thirdinterconnections;

[0077] forming a second conductor layer on the first insulating film andpatterning the second conductor layer to form one of the electrodes ofeach information storage capacitor independently for each memory cell;

[0078] forming a third conductor layer on the one electrode of theinformation storage capacitor and patterning the third conductor to formthe other electrode of the information storage capacitor commonly usedfor the plurality of memory cells in the first portion and to form afourth interconnection on the second interconnection in the, secondportion;

[0079] forming a second insulating film on the other electrode of theinformation storage capacitor and the fourth interconnection; and

[0080] forming a first connection hole in the second portion so that thefourth interconnection is exposed on the surface thereof in the secondinsulating film and also a second connection hole so that the thirdinterconnection is exposed on the surface thereof in the secondinsulating film, wherein the second interconnection is positioned belowthe first connection hole.

BRIEF DESCRIPTION OF THE DRAWINGS

[0081]FIG. 1 is a plan view showing the entirety of a semiconductor chipforming a DRAM in accordance with Embodiment 1 of the invention;

[0082]FIG. 2 is an enlarged plan view of the semiconductor chip forminga DRAM according to the Embodiment 1 of the invention;

[0083]FIG. 3 is a sectional view of an essential part of a semiconductorsubstrate showing a method for manufacturing a DRAM according to theEmbodiment 1 of the invention;

[0084]FIG. 4 is a plan view showing the respective patterns of conductorlayers constituting a memory cell and of a MISFET of a peripheralcircuit of a DRAM;

[0085]FIG. 5 is a schematic circuit diagram showing part of each of amemory array and an adjacent peripheral circuit of a DRAM according tothe Embodiment 1 of the invention;

[0086] FIGS. 6 to 27 are, respectively, a sectional view of an essentialpart of a semiconductor substrate illustrating, step by step, a methodfor manufacturing a DRAM according to the Embodiment 1 of the invention;

[0087]FIG. 27 is a graph showing the relationship between the sheetresistance of a gate electrode (word line) of a DRAM manufacturedaccording to the Embodiment 1 of the invention and the rise-up time ofthe word line;

[0088] FIGS. 28 to 33 are, respectively, a sectional view illustrating amethod for manufacturing a DRAM according to Embodiment 2 of theinvention;

[0089] FIGS. 34 to 38 are, respectively, a sectional view illustrating amethod for manufacturing a DRAM according to Embodiment 3 of theinvention;

[0090] FIGS. 39 to 49 are, respectively, a sectional view illustrating amethod for manufacturing a DRAM according to Embodiment 4 of theinvention;

[0091] FIGS. 50 to 55 are, respectively, a sectional view illustrating amethod for manufacturing a DRAM according to Embodiment 5 of theinvention;

[0092] FIGS. 56 to 61 are, respectively, a sectional view illustrating amethod for manufacturing a DRAM according to Embodiment 6 of theinvention;

[0093]FIG. 62 is a plan view showing the manner of connection amongfirst to third layers of a peripheral circuit of a DRAM according to theEmbodiment 6 of the invention;

[0094]FIG. 63 is a plan view showing a fuse pattern of a redundantcircuit of a DRAM according to the Embodiment 6 of the invention; and

[0095]FIG. 64 is a plan view showing the manner of connection among theinterconnections of a one chip microcomputer according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0096] The embodiments of the invention are described in detail withreference to the accompanying drawings, in which like reference numeralsindicate like parts or members throughout the specification and whenonce illustrated, their illustrations may not be repeated in subsequentdrawings.

[0097] (Embodiment 1)

[0098]FIG. 1 is a plan view of the entirety of a semiconductor chiphaving a DRAM formed according to this embodiment, and FIG. 2 is anenlarged plan view of part of the chip.

[0099] A semiconductor chip 1A comprising single crystal silicon has amain surface on which there is a DRAM having a capacity, for example, of64 Mbits (megabits). As shown in FIG. 1, the DRAM is constituted ofeight split memory mats MM and peripheral circuits disposed therearound.Each memory mat MM having a capacity of 8 M bits (megabits) is furtherdivided into 16 memory arrays MARY as is particularly shown in FIG. 2.The memory arrays MARY are, respectively, constituted of memory cellsdisposed in a matrix and each having a capacity of 2 Kbits(kilobits)×256 bits=512 Kbits and are provided therearound withperipheral circuits, such as sense amplifiers SA and word drivers WD.

[0100]FIG. 3 is a sectional view of an essential part of a semiconductorsubstrate showing parts of a memory array of the DRAM and the adjacentperipheral circuit. FIG. 4 is a plan view showing the patterns ofconductor layers constituting a memory cell of the DRAM and also ofconductor layers constituting MISFETs of the peripheral circuit, andFIG. 5 is a circuit diagram showing part of a memory array of the DRAMand part of an adjacent peripheral circuit. In FIG. 3, the sectionalstructure of a pair of memory cells is shown. The sectional structuresof MISFETs indicated by Qn and Qp in FIGS. 4 and 5 are shown in FIG. 3.

[0101] The semiconductor substrate 1 comprising a p-type single crystalsilicon has a p-type well 2 commonly provided for the memory array MARYand a peripheral circuit, and an n-type well 3 for the peripheralcircuit. In this connection, however, it may be possible to separatelyprovide p-type wells 2 for the memory array MARAY and the peripheralcircuit, respectively, without use of any common p-type well. The p-typewell 2 and the n-type well 3, respectively, have a field oxide film 4for element isolation on the surfaces thereof. The p-type well 2 has ap-type channel stopper layer 5 in the inside thereof including the lowerportion of the field oxide film 4. The n-type well 3 also has an n-typechannel stopper layer 6 in the inside thereof.

[0102] In an active region of the p-type well 2 of the memory arrayMARY, memory cells are arranged in a matrix form. Each memory cell isconstituted of one memory cell section MISFET Qt and one informationstorage capacitor C formed above the MISFET Qt. More particularly, thememory cell has a stacked capacitor structure wherein the informationstorage capacitor C is provided over the memory cell selection MISFETQt. The memory cell selection MISFET Qt and the information storagecapacitor C are connected in series to form a memory cell.

[0103] The memory cell selection MISFET Qt is composed of a gate oxidefilm 7, a gate electrode 8A integrally formed with a word line WL, and asource region and a drain region (i.e. n-type semiconductor regions 9,9). The gate electrode 8A (word line WL) is constituted of a two-layerconductor film comprising a low resistance polysilicon film doped withan n-type impurity (e.g. P (phosphorus)) and a W silicide (WSi₂) film,or a three-layer conductor film wherein a low resistance polysiliconfilm, a TiN (titanium nitride) film and a W film are built up in thisorder. The gate electrode 8A has a sheet resistance of 2 Ω/□ or below. Asilicon nitride film 10 is formed over the gate electrode 8A, and a sidewall spacer film 10 made of silicon nitride is formed at side walls ofthe gate electrode 8A. These insulating films (i.e. the silicon nitridefilm 10 and the side wall spacers 11) may be constituted of a siliconoxide film in place of the silicon nitride film.

[0104] In the active region of the p-type well of the peripheralcircuit, an n channel-type MISFET Qn is formed. A p channel-type MISFETQp is formed in the active region of the n-type well 3. Moreparticularly, the peripheral circuit is constituted of a CMOS(complementary metal oxide semiconductor) obtained by combination of then channel-type MISFET Qn and the p channel-type MISFET Qp.

[0105] The n channel-type MISFET Qn is composed of a gate oxide film 7,a gate electrode 8B, and a source region and a drain region. The gateelectrode 8B is constituted of a conductor film similar to that of thegate electrode 8A (word line WL) of the memory cell selection MISFET Qt,with its sheet resistance being 2 Ω/□ or below. A silicon nitride film10 is formed over the gate electrode 8B, and side wall spacers 11 madeof silicon nitride are formed at side walls of the gate electrode 8B asshown in FIG. 3. The source and drain regions of the n channel-typeMISFET Qn, respectively, have an LDD (lightly doped drain) structurewhich consists of an n⁻-type semiconductor region 12 with a low impurityconcentration and an n⁺-type semiconductor region 13 with a highimpurity concentration. The n⁺-type semiconductor region 13 has a Tisilicide (TiSi₂) layer 16 on the surface thereof.

[0106] The p channel-type MISFET Qp is constituted of a gate oxide film7, a gate electrode 8C, and a source region and a drain region. The gateelectrode 8C is constituted of a conductor film similar to that of thegate electrode 8A (word line WL) of the memory cell selection MISFET Qt,with its sheet resistance being 2 Ω/□ or below. A silicon nitride film10 is formed over the gate electrode 8C, and sidewall spacers 11composed of silicon nitride are formed at side walls of the gateelectrode 8C. The source and drain regions of the p channel-type MISFETQp, respectively, have an LDD structure which consists of a p⁻-typesemiconductor region 14 with a low impurity concentration and a p⁺-typesemiconductor region 15 with a high impurity concentration. The p+-typesemiconductor region 15 has a Ti silicide (TiSi₂) layer 16 on thesurface thereof.

[0107] A silicon oxide film 17, a BPSG (boron-doped phosphosilicateglass) film 18 and a silicon oxide film 19 are formed over the memorycell selection MISFET Qt, the n channel-type MISFET Qn and the pchannel-type MISFET Qp in this order.

[0108] Bit lines BL (BL₁, BL₂) are formed on the silicon oxide film 19of the memory array MARY. The bit lines BL₁, BL₂ are, respectively,constituted of a two-layer conductor film wherein a TiN film and a Wfilm are built up, with their sheet resistance being 2 Ω/□ or below. Thebit line BL₁ is electrically connected to one of the source region andthe drain region (n-type semiconductor region 9) of the memory cellselection MISFET Qt via a connection hole 21 in which a P or As-dopedpolysilicon plug 20 is placed or embedded. The bit line BL₂ iselectrically connected to one of the source region and the drain region(n⁺-type semiconductor region 13) of the n channel-type MISFET Qn of theperipheral circuit through a connection hole 23 but without use of anypolysilicon plug. The n⁺-type semiconductor region 13 of the nchannel-type MISFET Qn has a Ti silicide layer 16 of low resistance onthe surface thereof, so that the contact resistance with the bit lineBL₂ is reduced.

[0109] First interconnection layers 30A, 30B are formed over the siliconoxide film 19 of the peripheral circuit. The interconnections 30A, 30Bare, respectively, composed of a two-layer conductor film, like the bitlines BL₁, BL₂, wherein a TiN film and a W film are built up. The sheetresistance of the interconnections is 2 Ω/□ or below. Theinterconnection 30A is electrically connected at one end thereof to theother of the source region and the drain region (n⁺-type semiconductorregion 13) of the n channel-type MISFET Qn through a connection hole 24.The other end of the interconnection 30A is electrically connected toone of the source region and the drain region (p⁺-type semiconductorregion 15) of the p channel-type MISFET Qp via a connection hole 25. Theinterconnection 30B is electrically connected at one end thereof to theother of the source region and the drain region (p⁺-type semiconductorregion 15) of the p channel-type MISFET Qp via a connection hole 26. Alow resistance Ti silicide layer 16 is formed on the surface of then⁺-type semiconductor region 13 of the n channel-type MISFET Q and thesurface of the p⁺-type semiconductor region of the p channel-type MISFETQp. By this, the contact resistances of the interconnections 30A, 30Bare reduced.

[0110] A silicon nitride film 27 is formed on the bit lines BL₁, BL₂ andthe interconnections 30A, 30B, and side wall spacers 29 consisting ofsilicon nitride are formed at side walls of the bit lines BL₁, BL₂ andthe interconnections 30A, 30B. An SOG (spin on glass) film (insulatingfilm) 31 and a silicon oxide (insulating film) 32 are further formedover the bit lines BL₁, BL₂ and the interconnections 30A, 30B,respectively. Information storage capacitors C each including a storageelectrode (lower electrode) 33, a capacitance insulating film 24 and aplate electrode (upper electrode) 35 are formed on the oxide siliconfilm 32 of the memory array MARY.

[0111] The storage electrode 33 of the information storage capacitor Cis formed of a W film and is electrically connected to the other of thesource region and the drain region (n-type semiconductor region 9) ofthe memory cell selection MISFET Qt via a connection hole 37 embedding apolysilicon plug 36 therein and a connection hole 22 embedding apolysilicon plug 20 therein. The capacitance insulating film 34 is madeof a Ta₂O₅ (tantalum oxide) film, and the plate electrode is made of aTiN film.

[0112] A silicon oxide (insulating film) 38, a SOG film (insulatingfilm) 39 and a silicon oxide film (insulating film) 40 are formed on theinformation storage capacitors C in this order. A Y select line YS andsecond interconnection layers 41A, 41B of the peripheral circuit are,respectively, formed on the silicon oxide film 40 as shown. Theinterconnection 41A is electrically connected to the plate electrode 35via a connection hole 42 made at the insulating films (i.e. the siliconoxide film 40, the SOG film 39 and the silicon oxide film 28) which havebeen formed on the plate electrode 35 of the capacitor C, by which aplate potential (Vdd/²: a potential corresponding to a half of anapplied voltage Vdd from outside of the semiconductor chip) is suppliedto the plate electrode 35. The interconnection 41B is electricallyconnected to the interconnection 30B via a connection hole 43 made atthe insulating films (i.e. the silicon oxide film 40, the SOG film 39,the silicon oxide film 38, the silicon oxide film 32, the SOG film 31and the silicon nitride film 27) which have been formed over the firstinterconnection layer 30B of the peripheral circuit. A tungsten (W) plug44 is embedded in the inside of the connection hole 42 for connectionbetween the interconnection 41A and the plate electrode 35 and also inthe connection hole 43 for connection between the interconnection 41Band the interconnection 30B, respectively. The Y select line YS and theinterconnections 41A, 41B are each made of a conductor film whose sheetresistance is smaller than those conductor films for the gate electrode8A (word line WL) and the gate electrodes 8B, 8C and also for the bitlines BL₁, BL₂ and the interconnections 30A, 30B. For instance, such aconductor film is constituted of a three-layer conductor film wherein aTiN film an Al (aluminum) alloy film containing Si (silicon) and Cu(copper), and a TiN film are built up in this order.

[0113] The Y select line YS and the interconnections 41A, 41B are formedthereon, for example, with a third interconnection layer of theperipheral circuit through a layer insulating film composed of athree-layer insulting film wherein a silicon oxide film, an SOG film anda silicon oxide film are built up. A passivation film composed of atwo-layer insulating film wherein a silicon oxide film and a siliconnitride film are built up is further formed on the third interconnectionlayer although the third interconnection layer and the passivation filmare not particularly shown in the figures.

[0114] The method for manufacturing a DRAM according to this embodimentof the invention will be described in detail with reference to FIGS. 6to 24.

[0115] As shown in FIG. 6, a field oxide film 4 is initially formed onthe surface of a p⁻-type semiconductor substrate 1 according to a LOCOSmethod. A p-type impurity (boron (B)) is subjected to ion implantationinto the semiconductor substrate 1 at a region in which a memory cell isto be formed (memory array MARY) and also at a region wherein an nchannel-type MISFET of a peripheral circuit thereby forming a p-typewell 2. Then, an n-type impurity (phosphorus (P)) is ion implanted intothe semiconductor substrate 1 at a region where a p channel-type MISFETof the peripheral circuit is to be formed thereby forming an n-type well3. A p-type impurity (B) is ion implanted into the p-type well 2 to forma p-type channel stopper layer 5. Likewise, an n-type impurity (P) ision implanted into the n-type well 3 to form an n-type channel stopperlayer 6.

[0116] The p-type well 2 and the n-type well 3 surrounded by the fieldoxide film 4 are formed with a gate oxide film 7 on the surfaces of therespective active regions according to a thermal oxidation method. Animpurity for controlling a threshold voltage (Vth) of the MISFET is ionimplanted into the p-type well 2 and the n-type well 3 through the gateoxide film 7. Among the ion implantation for forming the wells (i.e. thep-type well 2 and the n-type well 3), the ion implantation for formingthe channel stopper layers (i.e. the p-type channel stopper layer 5 andthe n-type channel stopper layer 6) and the ion implantation for thecontrol of the threshold voltage (Vth) of the MISFET, the ionimplantations using the same conduction type of impurity may be effectedby one step with use of the same photoresist mask. The ion implantationfor the control of the threshold voltage (Vth) of the memory cellselection MISFET Qt and the ion implantation for controlling thethreshold voltage (Vth) of the MISFET s (i.e. then channel-type MISFETQn and the p channel-type MISFET Qp) of the peripheral circuit may beseparately performed to independently control the values of thethreshold voltages (Vth) for individual MISFETs.

[0117] As shown in FIG. 7, gate electrodes 8A (word lines WL) of thememory cell selection MISFET Qt, a gate electrode 8B of an nchannel-type MISFET Qn and a gate electrode 8C of a p channel-typeMISFET Qp are formed, respectively. For example, the gate electrodes 8A(word lines WL) and the gate electrodes 8B, 8C are, respectively, formedin the following manner. An n-type polysilicon film, a WSi₂ film and asilicon nitride film 10 are successively deposited on the semiconductorsubstrate 1 according to a CVD technique, followed by etching through aphotoresist mask to make a desired pattern of these films therebyforming them at the same time. Alternatively, an n-type polysilicon filmmay be first deposited according to a CVD technique, followed by furtherdeposition of a TiN film and a W film by sputtering and then of asilicon nitride film 10 according to a CVD technique. These films arepatterned as desired through a photoresist mask to form the electrodessimultaneously. It should be noted that the TiN film is formed in orderto prevent a reaction between the polysilicon film and the W film. Whenthe gate electrode 8A (the word line WL), and the gate electrodes 8B, 8Care, respectively, constituted of a low resistance material, e.g. whenthey are made of a three-layer conductor film wherein a TiN film (or aWN (tungsten nitride) film) and a Ti silicide film are superposed on ann-type polysilicon film, the sheet resistance can be reduced to 2 Ω/□ orbelow, preferably 1 Ω/□ or below.

[0118] As shown in FIG. 8, an n-type impurity (P) is ion implanted intothe p-type well 2 to form an n-type semiconductor region 9 of the memorycell selection MISFET Qt and n⁻-type semiconductor regions 12 of the nchannel-type MISFET Qn as self-aligned relative to the gate electrodes8A, 8B. A p-type impurity (B) is ion implanted into the n-type well toform p-type semiconductor regions 14 of the p channel-type MISFET Qp asself-aligned relative to the gate electrode 8C. It should be noted thatthe ion implantation for forming the n-type semiconductor regions 9, 9of the memory cell MISFETs Qt and the ion implantation for forming then⁻ semiconductor regions 12 of the n channel-type MISFET Qn may beseparately carried out so that the source region and the drain regionhave different impurity concentrations for the respective MISFETs.

[0119] As shown in FIG. 9, a side wall spacer 11 is formed on therespective side walls of the gate electrodes 8A (the word lines WL) ofthe memory cell selection MISFETs Qt, the gate electrode 8B of the nchannel-type MISFET and the gate electrode 8C of the p channel-typeMISFET. The side wall spacer 11 is formed through anisotropic etching ofa silicon nitride film deposited by a CVD technique. Thereafter, ann-type impurity (P) is ion implanted into the p-type well 2 of theperipheral circuit to form n+-type semiconductor regions of the nchannel-type MISFET Qn in self-aligned with the side wall spacer 11.Likewise, a p-type impurity (B) is ion implanted into the n-type well 3to form p⁺-type semiconductor regions 15 of the p channel-type MISFET Qnin self-aligned with the side wall spacer 11. Both or either of thesource region and the drain region of the n channel-type MISFET Qn andthe source region and the drain region of the p channel-type MISFET Qpwhich constitute the peripheral circuit may be constituted, ifnecessary, of a single drain structure or a double diffused drainstructure.

[0120] As shown in FIG. 10, a silicon oxide film 17 and a BPSG film 18are, respectively, deposited over the gate electrodes 8A (the word linesWL) of the memory cell selection MISFETs Qt, the gate electrode 8B ofthe n channel-type MISFET Qn and the gate electrode 8C of the pchannel-type MISFET Qp according to a CVD method, followed by polishingthe BPSG film by a chemical mechanical polishing (CMP) method to flattenthe surface thereof.

[0121] As shown in FIG. 11, a polysilicon film 28 is deposited on theBPSG film 18 according to a CVD method, and the polysilicon film 28 isetched through a photoresist mask, followed by further etching of theBPSG film 18, the silicon oxide film 17 and the gate oxide film 7 usingthe polysilicon film 28 as a mask. Consequently, a connection hole 21 isformed above one of the source region, and the drain region (the n-typesemiconductor region 9), and a connection hole 22 is formed above theother region (n-type semiconductor region 9).

[0122] Because the etching rates of the silicon nitride film 10 formedon the gate electrodes 8A (the word lines WL) of the memory cellselection MISFET Qt and the silicon nitride side wall spacers 11 formedon the side walls differ from that of the silicon oxide-based insulatingfilms (i.e. the BPSG film 18, the silicon oxide film 17 and the gateoxide film 7), they are left as being not etched. More particularly, agas used for the dry etching in order to form the connection holes 21,22 permits the silicon oxide to be etched at a greater rate and thesilicon nitride film to be etched at a smaller rate. By this means, fineconnection holes 21, 22 (i.e. regions contacting with the n-typesemiconductor region 9) which have a diameter smaller than a resolutionof exposing light used for making a photoresist mask can be formedself-alignedly to the sidewall spacers 11, enabling one to reduce thesize of the memory cell.

[0123] As shown in FIG. 12, a polysilicon plug 20 is placed in theinside of each of the connection holes 21, 22. The plug 20 is formed bydepositing a polysilicon film on the polysilicon film 28 according to aCVD method, followed by etching back the thus deposited polysilicon filmformed above the BPSG film 18. At the same time, the polysilicon film 28used as an etching mask is simultaneously removed. The polysilicon filmused as the plug 20 is doped with an n-type impurity (P). This impurityis diffused into the n-type semiconductor regions 9, 9 (i.e. the sourceregion and the drain region) of the memory cell selection MISFET Qtthrough the connection holes 21, 22, thereby forming semiconductorregions having an impurity concentration higher than the n-typesemiconductor regions 9, 9 although not shown in the figure.

[0124] As shown in FIG. 13, a silicon oxide film 19 is deposited overthe BPSG film 18 according to a CVD method. A photoresist which coversthe region of the peripheral circuit and has a through-hole at aconnection portion of a bit line BL₁ is formed as a mask, followed byetching to remove the silicon oxide 19 from above the connection hole21, thereby exposing a portion of the plug 20 where the bit line BL₁ isto be formed. As shown in FIG. 14, a photoresist which covers a memorycell-forming region and through-holes in the peripheral circuit regionis formed as a mask, followed by etching the silicon oxide film 19, theBPSG film 18, the silicon oxide 17 and the gate oxide film 7 of theperipheral circuit. In this manner, a connection hole 23 is formed untilone of the source region and the drain region (i.e. the n⁺-typesemiconductor region 13) of the n channel-type MISFET Qn is exposed, anda connection hole 24 is formed so that the other region (i.e. then⁺-type semiconductor region 13) is exposed. At the same time, aconnection hole 25 is formed so that one of the source region and thedrain region (i.e. the p⁺-type region 15) of the p channel-type MISFETQp is exposed, and a connection hole 26 is formed above the other region(i.e. the p⁺-type semiconductor region 15).

[0125] As shown in FIG. 15, a titanium silicide layer 16 is formed onthe surfaces of the n⁺-type semiconductor regions 13, 13 of the nchannel-type MISFET Qn exposed at the bottoms of the connection holes23, 24, on the surfaces of the p⁺-type semiconductor regions 15, 15 ofthe p channel-type MISFET Qp exposed at the bottom of the connectionholes 25, 26, and also on the surface of the plug 20 to which the bitline BL₁ is connected. The titanium silicide layer 16 is formed bydepositing a Ti film by sputtering and annealing the Ti film, followedby reaction with the Si substrate (i.e. the n⁺-type semiconductor region13 and the p⁺-type semiconductor region 15) and the polysilicon andremoval of an unreacted Ti film (i.e. a Ti film on the silicon oxidefilm 19) by wet etching. The formation of the titanium silicide layer 16results in a reduction of the contact resistance of the n⁺-typesemiconductor regions 13, 13 of the n channel-type MISFET Qn, thep⁺-type semiconductor regions 15, 15 of the p channel-type MISFET Qp,and the plug 20 with interconnections in contact therewith.

[0126] As shown in FIG. 16, bit lines BL₁, BL₂ are formed on the siliconoxide film 19 of the memory array MARY, and first layer interconnections30A, 30B are formed on the silicon oxide film 19 of the peripheralcircuit. The bit lines BL₁, BL₂ and the interconnections 30A, 30B aresimultaneously formed by depositing a TiN film and a W film on thesilicon oxide film 19 by sputtering, further depositing a siliconnitride film 27 by a CVD method, and etching these films by use of aphotoresist mask to make a desired pattern of these films. The bit linesBL₁, BL₂ and the interconnections 30A, 30B are, respectively, formed ofa low resistance material such as a two-layer conductor film wherein aTiN film (or a WN film) and a titanium silicide film are, for example,built up. By this, the sheet resistance can be reduced to a level of 2Ω/□ or below, preferably 1 Ω/□ or below.

[0127] As shown in FIG. 17, a silicon nitride film deposited by a CVDmethod is anisotropically etched to form side wall spacers 29 on theside walls of the bit lines BL₁, BL₂ and the interconnections 30A, 30B.Subsequently, a SOG film 31 is spin coated over the bit lines BL₁, BL₂and the interconnections 30A, 30B, followed by further deposition of asilicon oxide film according to a CVD method. It will be noted that whena silicon oxide film is used in place of the silicon nitride film 27 andthe side wall spacer 29 made of the silicon nitride film, the parasiticcapacitance of the bit lines BL₁, BL₂ and the interconnections 30A, 30Bcan be reduced.

[0128] As shown in FIG. 18, the silicon oxide film 32 and the SOG film31 are etched using a photoresist mask to form a connection hole 37above the connection hole 22 formed above the other of the source regionand the drain region (i.e. the n-type semiconductor region 9) of thememory cell selection MISFET Qt, respectively.

[0129] Even when the position of the connection hole 37 is shifted fromjust above the connection hole 22 as a result of misregistration of thephotoresist mask, as shown in FIG. 19, the silicon nitride film 27 whichhas been formed on the bit lines BL₁, BL₂ and the interconnections 30A,30B and the silicon nitride side wall spacers 29 formed on the sidewalls are left almost non-etched because the etching speed differs fromthat of the silicon oxide-based insulating films (i.e. the silicon oxidefilm 32 and the SOG film 31). Accordingly, even if an allowance for themask registration for the connection hole 37 and the connection hole 22is made small, the bit lines BL₁, BL₂ are not exposed at the time of theformation of the connection hole thereby preventing the short circuitingbetween the bit line BL₁ and the information storage capacitor C. Thisenables one to reduce the size of the memory cell. If a silicon oxidefilm is employed instead of the silicon nitride film 27 and the sidewall spacer 29 made of a silicon nitride film, it is necessary toprovide a space sufficient for mask registration between the connectionhole 37 and the side wall spacer 29.

[0130] As shown in FIG. 20, after embedding a plug 36 made of W in theconnection hole 37, a storage electrode 33 of an information storagecapacitor C is formed over the connection hole 37. The plug 36 is formedby etching back a W film (or a polysilicon film) deposited on thesilicon oxide 32 by a CVD method. The storage electrode 33 is formed byetching a W film, which is deposited on the silicon oxide film 32 bysputtering, through a photoresist mask in a desired pattern. The plug 36may be constituted of a polysilicon film or a builtup film of a TiN filmand a W film. The storage electrode 33 may be made of a film of a metalor a conductive metal oxide such as Pt, Ir, 1r0₂, Rh, RhO₂, Os, OSO₂,Ru, RuO₂, Re, ReO₃, Pd, Au and the like.

[0131] As shown in FIG. 21, a tantalum oxide film 34A is deposited onthe storage electrodes 33 according to a plasma CVD method, on which aTiN film 35A is further deposited by a CVD method. Thereafter, as shownin FIG. 22, these films are patterned by etching through a photoresistmask to form an information storage capacitor C including the storageelectrode 33 made of the W film, a capacitance insulating film 34 madeof the tantalum oxide film 34 and a plate electrode 35 made of the TiNfilm 35A. The storage electrode 33 is favorably formed to be so thickthat the capacitance of the information storage capacitor C becomesgreat. The plate electrode 35 is formed of the TiN film 35A. If thisfilm is formed to be too thick, the following problems arise: (1) theTiN film 35A is apt to suffer cracking therein; and (2) a stress isexerted on the capacitance insulating film 34 formed below, therebydegrading the characteristics of the film 34. Accordingly, the TiN filmpreferably has a thickness of approximately 0.2 μm. The capacitanceinsulating film 34 may be constituted of highly dielectric materialssuch as BST ((Ba, Sr)TiO₃), and ferroelectric materials such as PZT(PbZr_(x)T₁−XO₃), PLT (PbLa_(x)T₁—XO₃), PLZT, PbTiO₃, SrTiO₃, BaTiO₃,PbZrO₃, LiNbO₃, Bi₄Ti₃O₁₂, BaMgF4, Y1-based (SrBi₂(Nb,Ta)2O₉) and thelike. The plate electrode 35 may be constituted of films of metals orconductive metal oxides such as tungsten silicide/TiN, Ta, Cu, Ag, Pt,Ir, IrO₂, Rh, RhO₂, Os, OsO₂, Ru, RuO₂ Re, ReO₃, Pd, Au and the like.

[0132] As shown in FIG. 23, a silicon oxide film 38 is deposited overthe information storage capacitor C according to a CVD method and an SOGfilm 39 is spin coated on the film 38, followed by further deposition ofa silicon oxide film 40 by a CVD method. Subsequently, the insulatingfilms (i.e. the silicon oxide film 40, the SOG film 39 and the siliconoxide film 38) provided over the plate electrode 35 of the informationstorage capacitor C are selectively removed by etching to form aconnection hole 42. At the same time, the insulating films (i.e. thesilicon oxide film 40, the SOG film 39, the silicon oxide film 38, thesilicon oxide film 32, the SOG film 31 and the silicon nitride film 27)over the first interconnection layer 30B of the peripheral circuit areselectively etched to form a connection hole 43.

[0133] As shown in FIG. 24, tungsten (W) plugs 44 are respectively,embedded in the connection holes 42, 43. The plug 44 is formed bydepositing a W film on the silicon oxide film 40 by a CVD method andetching it back. The plug 44 may be constituted of a builtup film of aTiN film and a W film.

[0134] Thereafter, a Y select line YS and second interconnection layers41A, 41B are formed on the silicon oxide film 40, thereby approximatelycompleting the DRAM shown in FIG. 3. The Y select line YS and theinterconnections 41A, 41B are, respectively, formed simultaneously bydepositing a TiN film, an Al alloy film and a TiN film on the siliconoxide film 40 by sputtering, and patterning these films by etchingthrough a photoresist mask. The Y select line YS and theinterconnections 41A, 41B may be formed of a builtup film of a TiN filmand a Cu film, respectively.

[0135] It will be noted that in the step of forming the connection hole42 over the information storage capacitor C and the connection hole 43over the interconnection 30B of the peripheral circuit (as shown in FIG.23), the thickness of the insulating films on the interconnection 30B ismuch greater than that of the insulating films formed over theinformation storage capacitor C, with the great possibility that theplate electrode 35 exposed at the bottom of the connection hole 42 isetched off. To avoid this, when the tantalum film 34A and the TiN film35A deposited on the storage electrode 33 are patterned to form theinformation storage capacitor C, the silicon oxide film 32 and the SOGfilm 31 provided below the storage electrode 33 are etchedself-alignedly to the plate electrode 35, so that the insulating filmsprovided above the interconnection 30B are made thin. This makes only asmall difference between the thickness (A) of the insulating filmsprovided over the capacitor C and the thickness (B) of the insulatingfilms provided over the interconnection 30B. Thus, the inconvenience ofetching off the plate electrode 35 at the bottom of the connection holecan be prevented.

[0136] According to the above-stated embodiment of the invention, thefollowing advantages and features can be attained.

[0137] (1) The gate electrode 8A (the word line WL) of the memory cellselection MISFET Qt, the gate electrode 8B of the n channel-type MISFETQn of the peripheral circuit and the gate electrode 8C of the pchannel-type MISFET Qp are each made of a low resistance conductor filmwith its sheet resistance being 2 Ω/□ or below, permitting the gatedelay to be reduced. Thus, the working speed of the DRAM increases. Alow resistance metallic interconnection (i.e. a word line for shunt) forgate electrode backing, which is conventionally formed on theinformation storage capacitor, is not necessary, so that theinterconnection layers of the memory array MARY can be reduced by onelayer.

[0138] (2) In view of the above (1), the number of memory cellsconnecting to one word line can be increased. More particularly, thenumbers of word drivers WD and word decoders connected to a given numberof memory cells can be reduced, and this leads to a correspondinglyreduced chip size (or an enlarged area for memory arrays MARY) therebyimproving the degree of integration of the DRAM.

[0139]FIG. 27 is a graph showing the relation between the sheetresistance (Ω/□) of a word line and the time before the word line risesup from an input of an address decode signal (50%) to 90%. For instance,in order to realize RAS (raw address strobe) access time (tRAS)=30 nm(corresponding to a word line rise-up time=6.5 nm), it is sufficientthat the sheet resistance of a word line is about 8 Ω/□ in a case where256 memory cells are connected to a pair of word lines. In contrast,when the chip size is reduced by 5% while connecting 512 memory cellsper one word line, it is necessary for the sheet resistance of the wordline to be about 2 Ω/□ or below. This value does not change even whenthe minimal processing dimension of the memory cell is reduced. This isbecause the word line pitches and the bit line pitches are likewisereduced. According to the embodiment of the invention where the sheetresistance of the gate electrode 8A (the word line WL) is 2 Ω/□ orbelow, the chip size can be reduced by increasing the number of memorycells connected to one word line.

[0140] (3) Since the bit lines BL₁, BL₂ are constituted of a lowresistance conductor film and have a sheet resistance of 2 Ω/□ or below,the interconnections 30A, 30B of the peripheral circuit can be formedsimultaneously with the formation of the bit lines BL₁, BL₂.Accordingly, one step can be reduced for the formation of theinterconnections of the peripheral circuit.

[0141] (4) The first interconnection layers 30A, 30B connected to the nchannel-type MISFET Qn and the p channel-type MISFET Qp of theperipheral circuit are provided at a position lower than the informationstorage capacitor C for the memory cells. The aspect ratios of theconnection holes 23, 24 formed over the source region and the drainregion of the n channel-type MISFET Qn and the connection holes 25, 26formed over the source region and the drain region of the p channel-typeMISFET Qp can be made small. Thus, the connection reliability of theinterconnections in the connection holes can be improved.

[0142] (5) In view of (1) and (3) above, the interconnection layers ofthe memory array MARY can be reduced by one layer and theinterconnection layers of the peripheral circuit can also be reduced byone layer. The steps of manufacturing DRAM can be reduced in number withan improved yield and with a reduction of manufacturing costs.

[0143] (Embodiment 2)

[0144] In the method for manufacturing DRAM according to thisembodiment, the interconnections of the peripheral circuit are formedsimultaneously with the step of forming the gate electrode 8A (the wordline WL) of memory cell selection MISFET Qt, the gate electrode 8B ofthe n channel-type MISFET Qn of the peripheral circuit, and the gateelectrode 8C of the p channel-type MISFET Qp. The interconnection of theperipheral circuit is also formed simultaneously with the step offorming the bit lines BL₁, BL₂.

[0145] For the manufacture of a DRAM, as shown in FIG. 28, a field oxidefilm 4, a p-type well 2, an n-type well 3, a p-type channel stopperlayer 5 and an n-type channel stopper 6 are formed on the main surfaceof a semiconductor substrate 1 in the same manner as in Embodiment 1. Agate oxide film is formed on the respective active regions of the p-typewell 2 and the n-type well 3 surrounded by the field oxide film 4,followed by formation of a gate electrode 8A (a word line WL) of thememory cell selection MISFET Qt, a gate electrode 8B of an nchannel-type MISFET Qn, a gate electrode 8C of a p channel-type MISFETQp, and a first interconnection layer 8D. The gate electrode 8A (theword line WL), the gate electrodes 8B, 8C and the interconnection 8D areformed of the same low resistance conductor film as the gate electrode8A (the word line WL) and the gate electrodes 8B, 8C of Embodiment 1,with their sheet resistance being 2 Ω/□ or below.

[0146] As shown in FIG. 29, an n-type impurity (P) is ion implanted intothe p-type wells 2 to form an n-type semiconductor region 9 of thememory cell selection MISFET Qt and an n⁻-type semiconductor region 12of the n-channel-type MISFET Qn, both self-alignedly to the gateelectrodes 8A and 8B, respectively. A p-type impurity (B) is ionimplanted into the n-type well 3 to form a p⁻-type semiconductor region14 of the p channel-type MISFET Qp self-alignedly to the gate electrode8C.

[0147] As shown in FIG. 30, after formation of silicon nitride, sidewall spacers 11 on the respective side walls of the gate electrode 8A(the word line WL) of the memory cell selection MISFET Qt, the gateelectrode 8B of the n channel-type MISFET Qn, the gate electrode 8Cofthe p channel-type MISFET Qp, and the interconnection 8D, an n-typeimpurity (P) is ion implanted into the p-type well of the peripheralcircuit to form an n⁺-type semiconductor region 13 of the n channel-typeMISFET Qn as being self-aligned relative to the side wall spacer 11. Ap-type impurity (B) is ion implanted into the n-type well 3 to form ap⁺-type semiconductor region 15 of the p channel-type MISFET Qn as beingself-aligned relative to the side wall spacer 11.

[0148] As shown in FIG. 31, a silicon oxide film 17 and a BPSG film 18are deposited over the gate electrode 8A (the word line WL) of thememory cell selection MISFET Qt, the gate electrode 8B of the nchannel-type MISFET Qn, the gate electrode 8C of the p channel-typeMISFET Qp, and the interconnection 8D. Thereafter, connection holes 21,22 are formed over the source region and the drain region (n-typesemiconductor regions 9, 9) of the memory cell selection MISFET Qt,respectively. A polysilicon plug is embedded in the connection holes 21,22, respectively. The plug 20 may be formed in the same manner asillustrated with reference to FIGS. 11 and 12.

[0149] As shown in FIG. 32, a silicon oxide film 19 is deposited on theBPSG film 18, followed by removal of the silicon oxide film 19 above theconnection hole 21 by etching through a photoresist mask. Then, thesilicon oxide film 19, the BPSG film 18, the silicon oxide film 17 andthe gate oxide film 7 of the peripheral circuit are selectively etchedthrough a photoresist mask, thereby forming a connection hole 23 aboveone of the source region and the drain region of the n channel-typeMISFET Qn and a connection hole 24 above the other region. At the sametime, a connection hole 25 is formed above one of the source region andthe drain region of the p channel-type MISFET Qp and a connection hole26 is formed above the other region along with a connection hole 46above the interconnection 8D. This step is similar to that illustratedhereinbefore with reference to FIGS. 13 to 15.

[0150] As shown in FIG. 33, a titanium silicide layer is, respectively,formed on the surfaces of the n⁺-type semiconductor regions 13 of the nchannel-type MISFET Qn exposed at the bottoms of the connection holes23, 24 and the surfaces of the p⁺-type MISFET Qp exposed at the bottomsof the connection holes 25, 26. Bit lines BL₁, BL₂ are formed on thesilicon oxide layer 19 of the memory array MAR and secondinterconnection layers 30A, 30B are also formed on the silicon oxidelayer 19 of the peripheral circuit. The interconnection 30B iselectrically connected to the first interconnection layer 8D via theconnection hole 46. The bit lines BL₁, BL₂ and the interconnections 30A,30B are each formed of such a low resistance conductor film as the bitlines BL₁, BL₂ and the interconnections 30A, 30B of Embodiment 1, withtheir sheet resistance being 2 Ω/□ or below. This formation step issimilar to that illustrated with reference to FIG. 16.

[0151] Although not particularly shown in FIG. 33, an informationstorage capacitor C formed over the bit lines BL₁, BL₂ is formed in thesame manner as in Embodiment 1, followed by formation of a Y select lineand also of a third interconnection line of the peripheral circuit.

[0152] According to the method of manufacture of this embodiment, thefirst interconnection layer 8D of the peripheral circuit is formedsimultaneously with the formation of the gate electrode 8A (the wordline WL) of the memory cell selection MISFET Qt, and the gate electrode8B of the n channel-type MISFET Qn and the gate electrode 8C of the pchannel-type MISFET Qp of the peripheral circuit. The secondinterconnection layers 30A, 30B of the peripheral circuit aresimultaneously formed in the step of forming the bit lines BL₁, BL₂. Thethird interconnection layer of the peripheral circuit is formedsimultaneously with the formation of the Y select line. Thus, theinterconnections of the peripheral circuit can be formed by reducing twosteps, leading to a reduction in the number of the manufacturing stepsof the DRAM, an improved yield and the reduction of the manufacturingcosts.

[0153] (Embodiment 3)

[0154] In the method for manufacturing a DRAM according to thisembodiment, a semiconductor substrate 1 composed of p⁻-type singlecrystal is thermally oxidized to form a thin silicon oxide film 50 onthe surface thereof. A silicon nitride film 51 is deposited on thesilicon oxide film 50 according to a CVD method, followed by selectivelyetching the silicon nitride 51 through a photoresist mask to remove thesilicon nitride film 51 in element separation regions as shown in FIG.34.

[0155] As shown in FIG. 35, the semiconductor substrate 1 at the elementseparation regions is etched using the silicon nitride film 51 as a maskto form shallow grooves 52, followed by thermal oxidation of thesemiconductor substrate 1 to form a silicon oxide film 53 on the innerwalls of the grooves 52.

[0156] As shown in FIG. 36, a silicon oxide film 54 is filled in therespective shallow grooves 52. In order to fill the silicon oxide film54 in each groove 52, the silicon oxide film 54 is deposited over thesemiconductor substrate 1 by use of a CVD method, followed by polishingthe silicon oxide film 54 according to a chemical mechanical polishing(CMP) Method. Subsequently, the silicon nitride film 51 left on thesemiconductor substrate 1 is removed by etching.

[0157] As shown in FIG. 37, a p-type impurity (B) is ion implanted intoregions of the semiconductor substrate 1 where a memory cell is to beformed and where an n channel-type MISFET of a peripheral circuit is tobe formed, thereby forming a p-type well 2. An n-type impurity (P) ision implanted into a region of the semiconductor substrate 1, where a pchannel-type MISFET of the peripheral circuit is to be formed, therebyforming an n-type well 3. When ion implantation is carried out such thatdistribution peaks of the n-type impurity and the p-type impurity aresubstantially in coincidence with the depth of the shallow grooves 52,it becomes possible for the p-type well 2 to serve as a p-type channelstopper layer and the n-type well 3 to serve as an n-type channelstopper layer.

[0158] As shown in FIG. 38, the active regions of the p-type well 2 andthe n-type well 3 surrounded by the shallow grooves 52 are thermallyoxidized to form a gate oxide film 7. Subsequent steps are the same asthose of Embodiment 1.

[0159] According to this embodiment of the invention, the p-type well 2serves also as a p-type channel stopper and the n-type well 3 serves asan n-type channel stopper, so that the ion implantation step of forminga p-type channel stopper layer and the ion implantation step of formingan n-type channel stopper layer do not become necessary. Thus, thenumber of steps of manufacturing the DRAM can be reduced.

[0160] According to the method of this embodiment, the elements areseparated from each other by means of the shallow grooves formed in thesemiconductor substrate 1, permitting the DRAM to be made finer in size.Since there is no step between the element isolation region and theactive region, it becomes possible to avoid the problem that a conductorfilm, such as a gate electrode, deposited on the semiconductor substrate1, is made thinner at a stepped portion. It will be noted that theelement isolation method set out in Embodiment 3 is applicable to allthe embodiments of the invention.

[0161] (Embodiment 4)

[0162] The method for manufacturing DRAM according to this embodiment ofthe invention includes the simultaneous formation of interconnections ofa peripheral circuit in the step of forming a storage electrode (lowerelectrode) of an information storage capacitor C of a memory cell.

[0163] For the manufacture of the DRAM, as shown in FIG. 39, a gateelectrode 8A (the word line WL) of memory cell selection MISFET Qt, anda gate electrode 8B of an n channel-type MISFET Qn and a gate electrode8C of a p channel-type MISFET Qp of a peripheral circuit are formed onthe main surface of a semiconductor substrate 1 in the same manner as inEmbodiment 1. The gate electrode 8A (the word lines WL) and the gateelectrodes 8B, 8C are formed of a low resistance conductor film similarto those of the gate electrode 8A (the word line WL) and the gateelectrodes 8B, 8C of Embodiment 1, with their sheet resistance being 2Ω/□ or below.

[0164] As shown in FIG. 40, a silicon oxide film 17 and a BPSG film 18are deposited over the gate electrode 8A (the word line WL) of memorycell selection MISFET Qt, and the gate electrode 8B of the nchannel-type MISFET Qn and the gate electrode 8C of the p channel-typeMISFET Qp. Subsequently, the BPSG film 18, the silicon oxide film 17 andthe gate oxide film 7 are etched through a mask of a polysilicon film 28to form connection holes 21, 22 above the source region and the drainregion (i.e. the n-type semiconductor regions 9, 9) of the memory cellselection MISFET Qt. At the same time, a connection hole 23 is formedabove one of the source region (i.e. an n⁺-type semiconductor region 13)of the n channel-type MISFET Qn of the peripheral circuit to which a bitline (BL₂) is connected in a subsequent step.

[0165] As shown in FIG. 41, a polysilicon plug 20 is, respectively,embedded in the connection holes 21, 22, 23. Thereafter, as shown inFIG. 42, bit lines BL₁, BL₂ are formed on the silicon oxide film 19 ofthe memory array MARY. The bit lines BL₁, BL₂ are formed of a lowresistance conductor film similar to that of the bit lines BL₁, BL₂ ofEmbodiment 1, with their sheet resistance being 2 Ω/□ or below.

[0166] As shown in FIG. 43, a silicon nitride film deposited by a CVDmethod is anisotropically etched to form side wall spacers 29 on sidewalls of the bit lines BL₁, BL₂, followed by spin coating of an SOG film31 over the bit lines BL₁, BL₂ and then deposition of a silicon oxidefilm 32 by a CVD method.

[0167] As shown in FIG. 44, the silicon oxide film 32 and the SOG film31 are etched using a photoresist mask to form connection holes 37 abovethe connection hole 22 which has been formed on the other of the sourceregion and the drain region (i.e. the n-type semiconductor region 9) ofthe memory cell selection MISFET Qt. At the same time, the silicon oxidefilm 32, the SOG film 31, the BPSG film 18, the silicon oxide film 17and the gate oxide film 7 of the peripheral circuit are etched so that aconnection hole 24 is formed, along with a connection hole 25 formedabove one of the source region and the drain region (i.e. the p⁺semiconductor region 15) of the p channel-type MISFET Qp and aconnection hole 26 formed above the other region (i.e. the p⁺semiconductor region 15).

[0168] As shown in FIG. 45, a plug 47 made of a builtup film of a TINfilm and a W film is filled in the connection holes 37, 24, 25 and 26. Astorage electrode 33 of an information storage capacitor C is formed onthe connection hole 37 as shown in FIG. 46. At the same time, firstinterconnection layers 33A, 33B of the peripheral circuit are formed.The storage electrode 33 and the interconnections 33A, 33B are,respectively, formed of a low resistance conductor film similar to thestorage electrode 33 of Embodiment 1.

[0169] As shown in FIG. 47, a capacitance insulating film 33 and a plateelectrode 35 are formed on the storage electrode 33 to form aninformation storage capacitor C. A silicon oxide film 38 is depositedover the information storage capacitor C according to a CVD method asshown in FIG. 48, followed by spin coating of an SOG film 39 on the film38 and further deposition of a silicon oxide film 40 by a CVD method.Subsequently, using a photoresist mask, the insulating films (i.e. thesilicon oxide film 40, the SOG film 39 and the silicon oxide 38) overthe plate electrode 35 of the information storage capacitor C are etchedto form a connection hole 42. Simultaneously, the insulating films (i.e.the silicon oxide film 40, the SOG film 39 and the silicon oxide 38)over the first interconnection layer 33B of the peripheral circuit areetched to form a connection hole 43. A tungsten plug 44 is,respectively, filled in the connection holes 42, 43 as shown.

[0170] As shown in FIG. 49, a Y select line YS and secondinterconnection layers 41A, 41B of the peripheral circuit are formed onthe silicon oxide 40. The Y select line YS and the interconnections 41A,41B are made of a low resistance conductor film as used for the Y selectline YS and the interconnections 41A, 41B in Embodiment 1, and are made,for example, of a builtup film of a TiN film, an Al alloy film and a TiNfilm, or a builtup film of a TiN film and a Cu film.

[0171] According to the above method, the storage electrode 33 of thecapacitor C is made of a low resistance conductor film with its sheetresistance being 2 Ω/□ or below. This makes it possible to form theinterconnections 33A, 33B of the peripheral circuit simultaneously withthe formation of the storage electrode 33. Thus, an additional step offorming the interconnections of the peripheral circuit is not necessary.

[0172] In this embodiment of the invention, although the firstinterconnection layers 33A, 33B of the peripheral circuit are formedsimultaneously with the formation of the storage electrode of thecapacitor C, one step of forming the interconnections of the peripheralcircuit can be further reduced if the following procedures are used.More particularly, the first interconnection layers of the peripheralcircuit are formed simultaneously with the formation of the gateelectrodes 8A (the word lines WL) and the gate electrodes 8B, 8C, thesecond interconnection layer of the peripheral circuit is formedsimultaneously with the formation of the storage electrode of thecapacitor C, and the third interconnection layer of the peripheralcircuit is formed along with the formation of Y select line YS.

[0173] (Embodiment 5)

[0174] The method of manufacturing a DRAM according to this embodimentof the invention includes the formation of interconnections of aperipheral circuit simultaneously with the formation of a plateelectrode (an upper electrode) of an information storage capacitor C.

[0175] For the manufacture of this type of DRAM, as shown in FIG. 50,memory cell selection MISFET s Qt and an n channel-type MISFET Qn and ap channel-type MISFET Qp of a peripheral circuit are formed in the samemanner as in Embodiment 1, followed by simultaneous formation of bitlines BL₁, BL₂ and first interconnection layers 30A, 30B thereover. Astorage electrode 33 of an information storage capacitor C is furtherformed over the bit lines BL₁, BL₂. The gate electrode 8A (the word lineWL) and the gate electrodes 8B, 8C are formed of such a low resistanceconductor film as used for the gate electrode 8A (the word line WL) andthe gate electrodes 8B, 8C in Embodiment 1, with their sheet resistancebeing 2 Ω/□ or below.

[0176] As shown in FIG. 51, a tantalum oxide film 34 is deposited overthe storage electrode 33 according to a plasma CVD, followed by furtherdeposition of a TiN film by a CVD. As shown in FIG. 52, these films arethen patterned by etching via a photoresist mask to form a capacitanceinsulating film 34 and a plate electrode 35 on the respective storageelectrode 33, thereby forming information storage capacitors C. At thesame time, the tantalum film 34A and the TiN film 35A of the peripheralcircuit are also patterned to form a second interconnection layer 35B ofthe peripheral circuit.

[0177] Since the second interconnection layer of the peripheral circuitis constituted of a double-layer film wherein the conductive TiN film35A is formed on the insulating tantalum oxide film 34A, it cannot beconnected directly to the first interconnection layer (30B) of theperipheral circuit.

[0178] As shown in FIG. 53, a silicon oxide film 38 is deposited on thecapacitor C and the interconnection 35B by a CVD method, followed byspin coating of an SOG film 39 and further deposition of a silicon oxidefilm 40 by a CVD method on the film 38 in this order. Using aphotoresist mask, the insulating films (i.e. the silicon oxide film 40,the SOG film 39 and the silicon oxide film 38) formed on the plateelectrode 35 of the capacitor C are etched to form a connection hole 42.At the same time, the insulating films (i.e. the silicon oxide film 40,the SOG film 39 and the silicon oxide film 38) formed on theinterconnection 35A of the peripheral circuit are etched to form aconnection hole 48. Moreover, the insulating films (i.e. the siliconoxide film 40, the SOG film 39, the silicon oxide film 38, the siliconoxide film 32, the SOG film 31 and the silicon nitride film 27) formedover the first interconnection layer 30B of the peripheral circuit aresimultaneously etched to form a connection hole 43.

[0179] As shown in FIG. 54, a W plug 44 is, respectively, filled in theconnection holes 42, 43 and 48, after which a Y select line YS and thirdinterconnection layers 41A, 41B of the peripheral circuit are formed onthe silicon oxide film 40. The second interconnection layer of theperipheral circuit is electrically connected via the thirdinterconnection layer 41B to the first interconnection layer 30B.

[0180] According to this manufacturing method, the first interconnectionlayers 30A, 30B of the peripheral circuit are simultaneously formedduring the step of forming the bit lines BL₁, BL₂. The secondinterconnection layer 35B of the peripheral circuit is formed during thestep of forming the plate electrode 35 of the capacitor C, and the thirdinterconnection layer is simultaneously formed during the step offorming the Y select line. Thus, the two steps of forming theinterconnections of the peripheral circuit can be reduced.

[0181] In the step of forming the connection holes 42, 43 and 48 (FIG.53), the insulating films formed over the interconnection 30B is muchthicker than the insulating films over the capacitor C and over theinterconnection 35B. Hence, there is the great possibility that theplate electrode 35 exposed at the bottom of the connection hole 42 andthe interconnection 35B exposed at the bottom of the connection hole 48are etched off. To avoid this, a dummy gate DWL for reducing a stepdifference which is not employed as an actual gate electrode is providedbelow the interconnection 30B as shown in FIG. 55. By this, the aspectratio of the connection hole comes close to those of the connectionholes 42, 48, thereby preventing the inconvenience of etching off theplate electrode 35 at the bottom of the connection hole 42 and theinterconnection 35B at the bottom of the connection hole 48. As shown inFIG. 55, a dummy interconnection 30C which is not actually used as aninterconnection and is electrically floating may be formed below thesecond interconnection layer 35C electrically connected to the thirdinterconnection layer 41C through the connection hole 49. The dummyinterconnection 30C is formed simultaneously with the formation of thebit lines BL₁, BL₂ and the first interconnection layers 30A, 30B of theperipheral circuit. If the interconnection 35C is etched off at thebottom of the connection hole 49, the lower dummy interconnection 30Cserves as a stopper for etching. Thus, the connection hole 49 cannotbreak through up to the substrate. Moreover, if a dummy gate DWL isformed below the dummy interconnection 30C, the inconvenientbreaking-through of the connection hole 49 to the substrate is morereliably prevented. Thus, it is effective that since the interconnection35 cannot be formed as thick, such a dummy interconnection 30C and/or adummy gate DWL as set out above is formed below the connection hole 49or as surrounding the connection hole 49 therewith as viewed on theplane.

[0182] (Embodiment 6)

[0183] The method for manufacturing a DRAM according to this embodimentincludes simultaneous formation of the interconnections of theperipheral circuit in the step of forming the bit lines BL₁, BL₂ and inthe step of forming the plate electrode of the information storagecapacitor C, like Embodiment 5.

[0184] In order to manufacture the DRAM, the memory cell selectionMISFET Qt and the n channel MISFET Qn and the p channel-type MISFET Qpare formed in the same manner as in Embodiment 5, followed by formationof bit lines BL₁, BL₂ thereover (FIG. 50). At the time of the formationof the bit lines, the first interconnection layers 30D to 30G of theperipheral circuit are simultaneously formed as shown in FIG. 56. Thebit lines BL₁, BL₂ and the interconnections 30D to 30G are formed of alow resistance conductor film such as has been set out hereinbefore,with their sheet resistance being 2 Ω/□ or below.

[0185] As shown in FIG. 57, second interconnection layers 35C to 35F ofthe peripheral circuit are, respectively, formed over the firstinterconnection layers 30D to 30G of the peripheral circuit as shown inFIG. 57. The interconnections 35C to 35F are formed simultaneously withthe formation of the capacitance insulating film 34 and the plateelectrode 35 of the information storage capacitor C, with their sheetresistance being 2 Ω/□ or below. The interconnection 35C is positionedjust above the first interconnection layer 30D, and the interconnection35D is positioned just above the first interconnection layer 30E. Theinterconnection 35E is formed just above the first interconnection layer30F, and the interconnection 35F is formed just above the firstinterconnection layer 30G.

[0186] As shown in FIG. 58, a silicon oxide film 38 is deposited overthe interconnections 35C to 35F according to a CVD method, followed byspin coating of an SOG film 39 thereon and further deposition of asilicon oxide film 40 by a CVD method. Thereafter, as shown in FIG. 59,the insulating films formed on the first interconnection layers 30D to30G of the peripheral circuit and the second interconnection layers 35Cto 35F are selectively etched by use of a photoresist mask. As aconsequence, there are simultaneously formed a connection hole 56arriving at the first interconnection layer 30D through the secondinterconnection layer 35C, a connection hole 57 arriving at the firstinterconnection layer 30E through the second interconnection layer 35D,a connection hole 58 arriving at the first interconnection layer 30Fthrough the second interconnection layer 35E, and a connection hole 59arriving at the first interconnection layer 30G through the secondinterconnection layer 35F. In this etching procedure, the types ofmaterials to be etched and the thicknesses of the films aresubstantially the same for all the connection holes 56 to 59, neitherpermitting a non-etched residue to be left in the inside of any of theconnection holes 56 to 59, nor causing any of the first interconnectionlayers 30D to 30G to be etched off excessively.

[0187] As shown in FIG. 60, a tungsten plug 44 is embedded in each ofthe connection holes 56 to 59. Third interconnection layers 41D to 41Gof the peripheral circuit are formed on the silicon oxide film 40 asshown in FIG. 61. The structure at the left side of FIG. 61 is astructure of connection between the first interconnection layer 30D andthe second interconnection layer 35C. In this structure, the secondinterconnection layer 35C is electrically connected via the plug 44formed in the connection hole 56 to the first interconnection layer 30D.In this case, the third interconnection layer 41D is a dummyinterconnection which is not actually used and serves as a kind of capwhich covers the surface of the interconnection hole 56 over the secondinterconnection layer 35C. More particularly, when the thirdinterconnection layer is patterned, the third interconnection layer 41Dprotects the plug 44 from being etched. In this sense, the layer 41Dshould completely cover the connection hole 56 therewith on a plane.

[0188] The second structure as viewed from the left side of FIG. 61 is astructure for connection of the first interconnection layer 30E, thesecond interconnection layer 35D and the third interconnection layer41E. In this structure, the third interconnection layer 41E, the secondinterconnection layer 35D and the first interconnection layer 30E aremutually electrically connected via the plug 44 formed on the connectionhole 57. The third interconnection layer 41F is electrically connectedto the first interconnection layer 30F via the plug 44 formed in theconnection hole 58. In this case, the second interconnection layer 35Eis a dummy interconnection which is not actually used as aninterconnection. The third interconnection layer 41G is electricallyconnected to the second interconnection layer 35F via the plug 30Gformed in the hole 59. In this case, the first interconnection layer 30Gis a dummy interconnection not actually used. The dummy interconnections41D, 35E and 30G are those interconnections which are not connected toother interconnections in regions other than the portions of theconnection holes 56, 58, 59. Of course, the plug 44 is made of any typeof conductor materials.

[0189]FIG. 62 is a plan view showing an example of connection of thefirst to third interconnections of a peripheral circuit. In the figure,interconnections 41H, 41I are third interconnection layers constitutingelectric power lines, and interconnections 41J, 41K are thirdinterconnection layers constituting signal lines. All theinterconnections are formed by patterning from the same layer as a Yselect line YS. Interconnections 35G, 35H are second interconnectionlayers constituting signal lines and are formed by patterning from thesame layer as the plate electrode 35 of an information storage capacitorC. Interconnections 30H to 30K are first interconnection layers and areformed by patterning from the same layer as the bit lines BL₁, BL₂.

[0190] In this instance, a third dummy interconnection layer 41G isformed in a connection hole 60 for connection between a secondinterconnection layer 35H and a first interconnection layer 30I. Asecond dummy interconnection layer 35I is formed in a connection hole 61for connection between a third interconnection layer 41I and a firstinterconnection layer 30H. A first dummy interconnection layer 30L isformed in a connection hole 62 for connection between the thirdinterconnection layer 41J and the Y second interconnection layer 35H. Athird interconnection layer 41K, a second interconnection layer 35G anda first interconnection layer 30J are mutually connected via aconnection hole 63. It will be noted that the connection holes 60, 61,62 and 63 are so formed that they arrive at the first interconnectionlayer prior to the formation of the third interconnection layers.

[0191] As will be apparent from FIG. 61, according to the method of thisembodiment, there are simultaneously formed by one step the connectionhole (56) for electric connection between the second interconnectionlayer and the first interconnection layer of the peripheral circuit ofDRAM, the connection hole (57) for electric connection of the thirdinterconnection layer, the second interconnection layer and the firstinterconnection layer, the connection hole (58) for electric connectionbetween the third interconnection layer and the first interconnectionlayer, and the connection hole (59) for electric connection between thethird interconnection layer and the second interconnection layer. Forthe etching, the types of materials for films to be etched and the filmthicknesses should be substantially the same for all the connectionholes. By this, the connection holes can be formed under substantiallythe same conditions, ensuring improved reliability of the connections ofthe interconnections of the peripheral circuit. The secondinterconnection layers 35C to 35F of the peripheral circuit may beformed simultaneously with the formation of the storage electrode (lowerelectrode) of the information storage capacitor C.

[0192] In the method of this embodiment, although the interconnectionsof the peripheral circuit are formed simultaneously with the formationof the plate electrode (the upper electrode) of the capacitor C, aresistor element may also be formed at the same time.

[0193]FIG. 63 shows an example wherein fuses 35J of a redundant circuitwhich relieve defective bits are formed simultaneously with theformation of the plate electrode and the second interconnection layersof the peripheral circuit. In this instance, each fuse 35J iselectrically, connected at ends thereof with third interconnectionlayers 41M through connection holes 64. At the lower portion of theconnection holes, first dummy interconnection layers 30M are formed inorder to prevent the connection hole from breaking through thesubstrate.

[0194] The resistor element of the peripheral circuit may be formedsimultaneously with the formation of the storage electrode (the lowerelectrode) of the capacitor C. Alternatively, the resistor element maybe formed simultaneously with the formation of the bit lines BL₁, BL₂.

[0195] (Embodiment 7)

[0196] A DRAM is employed at a RAM portion of a one chip microcomputerforming a logic LSI such as CPU and a memory Sl on the samesemiconductor substrate. A one chip microcomputer shown in FIG. 64includes a DRAM of the invention at a RAM portion. This DRAM is made,like the DRAM of Embodiment 5, by forming first interconnection layersof a peripheral circuit simultaneously with the formation of lowresistance bit lines, forming second interconnection layers of theperipheral circuit simultaneously with the formation of a plateelectrode of an information storage capacitor, and further forming thirdinterconnection layers simultaneously with the formation of a Y selectline.

[0197] When using this type of DRAM at the RAM portion of the one chipmicrocomputer, the manufacturing process of the one chip microcomputercan be simplified with reduced manufacturing costs for the reason thatthe first interconnection layers, such as for the CPU unit and aninput/output (I/O) circuit, are formed simultaneously with the formationof the bit lines BL, the second interconnection layers (M2) are formedsimultaneously with the formation of the plate electrode, and the thirdinterconnection layers (M3) are formed simultaneously with the Y selectline.

[0198] Although various embodiments of the invention have beenparticularly described hereinabove, the invention is not limited tothose embodiments and various variations and modifications may bepossible without departing from the spirit of the invention.

[0199] The features and advantages of typical embodiments disclosedherein are briefly summarized below.

[0200] According to the invention, the interconnections of memory arraysand the interconnections of a peripheral circuit can be reduced innumber, so that the number of the steps of manufacturing the DRAM can bereduced with an improved yield and a reduced production cost.

[0201] Because the gate electrodes (word lines) can be made low inresistance according to the invention, word drivers and sense amplifiersconnected to a given number of memory cells can be reduced in number.This allows a reduced chip size and an improved degree of integration ofDRAM.

[0202] The first interconnection layers and the second interconnectionlayers connecting a n channel-type MISFET and a p channel-type MISFET ofa peripheral circuit are disposed below the information storagecapacitor of a memory cell. Thus, the aspect ratio of connection holesforme4 over the source and drain regions of these MISFET'S is madesmall, thereby improving the connection reliability of theinterconnections of the peripheral circuit.

What we claim is:
 1. A semiconductor integrated circuit devicecomprising: a semiconductor substrate containing a first region and asecond region; first MISFETs formed in said first region; second MISFETsformed in said second region, each of said second MISFETs having a gateelectrode and impurity regions; a first insulating layer formed oversaid first and second MISFETs; word lines formed over said first region;bit lines formed over said word lines and said first insulating layer,wherein each of said first MISFETs is included in an individual one ofplural memory cells, each of said memory cells being connected to one ofsaid bit lines and one of said word lines; a second insulating layerformed over said bit lines and first insulating layer, wherein saidfirst and second insulating layer having a hole formed therethrough; aplug formed in said hole; and a wiring layer formed over said secondinsulating film, said wiring layer being electrically connected to saidimpurity region via said plug.